A touch-sensing-enabled active matrix LCD display panel (or touchscreen) is an active matrix LCD panel having an additional function of detecting a location of a possible finger and/or pointing device touch made on the panel. A capacitive touchscreen comprises an insulator such as glass, coated with a transparent conductor. As the human body also conducts electricity, touching the surface of the screen results in a distortion of the screen's electrostatic field, measurable as a change in capacitance. Various technologies can then be used to detect the location of the touch point.
The detection may be done by an electrostatic capacitance method. In the art, it is known that parasitic capacitance in the panel affects the sensitivity in the touch detection. The effective parasitic capacitance is nonlinear and voltage-dependent. It is desirable to reduce the parasitic capacitance or the voltage dependency thereof.
In U.S. Patent Application Publication No. 2015/0084911, the effective parasitic capacitance experienced in touch sensing is reduced by configuring a second transistor to cause the parasitic capacitance to be between a gate line and a drain of the second transistor instead of between the gate line and a drain of a first transistor. In U.S. Patent Application Publication No. 2014/0043546, a stress-relief layer whose product of dielectric constant and specific gravity is smaller than that of a substrate is added to a touch sensor in order to reduce the parasitic capacitance. Although not directly related to parasitic-capacitance reduction, U.S. Pat. No. 8,933,895 teaches introducing an additional network of common-voltage electrodes arranged side by side on a display panel so that the touch detection sensitivity is increased while suppressing influence to the display operation.
The methods disclosed in these prior-art references require additional materials and/or circuitry components, thereby increasing the costs in the implementation of these methods. There is a need in the art to have a technique for reducing parasitic capacitance or its voltage dependency without considerably increasing the implementation complexity.